There has been an ever-increasing need for greater memory capacity and rapid data processing. There have been many significant advances with respect to the design of faster and more complex processors, application specific integrated circuits (ASICs), and the like. Such complex circuits sometimes take advantage of the use of multiple parallel processors and ancillary circuitry.
Often, attempts are made in circuit design and structure to limit the signal travel distance between processors, memories, and other ancillary components so that processor-operating speed is not unduly limited and rapid data processing and management can therefore be achieved. In fact, processor-operating speeds are sometimes reduced because of unavoidable signal travel distance requirements that can be imposed by the specific system's design. This is particularly true for the use of multiple high-speed processors with one or more essential ASICs.
Accordingly, as the clock frequency of electronics increases, the physical distant between components on a data path becomes more and more critical. This physical distance is particularly important between an integrated circuit such as an ASIC and a memory module such as a cache that is connected to the integrated circuit. The physical distance between such components will impact the access time and, therefore, the performance of the resulting circuit assembly.
One method of reducing the physical distance between an integrated circuit and its memory module is to stack the memory module with respect to the integrated circuit. Such stacking of the memory modules can also permit the manufacturer to partition the total memory module assembly into smaller, less expensive portions in order to provide improved configurability and upgrading.
Various attempts have been made in the past to utilize a stacked structure. U.S. Pat. No. 5,191,404 to Wu et al. describes a low-profile, high-density package for integrated circuit chips. First and second multilayer interconnect members, each having low-profile memory chips mounted thereon, are affixed to one another and low-profile edge clips are subsequently applied to connect the conductive portions of the interconnect members.
U.S. Pat. No. 5,613,033 to Swamy et al. describes an interconnect system in which one or more laminated modules embodying electrical devices can be stacked in a three dimensional configuration upon a printed circuit board. The laminated module includes an intermediate component with vias extending through it, a female component having vias extending through it, and a male component also having vias extending through it. The components include a solder coating that allows permanent fixture of the various components with respect to one another.
U.S. Pat. No. 5,701,233 to Carson et al. describes a stacked, multimodular circuit assembly including stacked, resealable, electronic circuit modules having embedded through-vias between their upper and lower surfaces. The stacked modules are electrically interconnected by interposing between adjacent modules a resealable, multi-channel connector array having electrically conductive channels coupled opposing through-vias in the adjacent modules.
Despite various prior attempts to stack circuit assemblies, there remains a need for improved circuit assemblies that can employ standard and commonly available components as well as known manufacturing techniques. Accordingly, it is an object of this invention to provide an improved stacked circuit assembly that is adapted for mounting memory modules such as RAM modules in close proximity to an integrated circuit such as an ASIC.